activar un display de 7 segmentos de ánodo común en donde la posición de cada barra forma el número decodificado. Circuito integrado () circuito integrado 1. CIRCUITO INTEGRADO Recommended. Teaching Techniques: Creating Effective Learning. SNAN. SNANE4. ACTIVE. PDIP. N. Green (RoHS. & no Sb/Br). CU NIPDAU. N / A for Pkg Type. 0 to SNAN. SN74LS47D. ACTIVE.

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The reproduction, ontegrado, microfilming as well as storing and processing of data in electronic systems are liable to prosecution. Illegal for sale outside the following countries: With more than “new entries” and the new AC and ACT technologies the compilation had to be split into “ttl 74’s” and infegrado 74’s”.

Section 1 “Functional Contents”: In this section you can locate the families suitable for handling a specific problem. The List of Kntegrado has been com- pletely revised and supplemented by indications as to sales openings and distributors throughout Europe.

Here, we have kept to the accepted concept of combining cjrcuito salient data such as abbreviations, data, comparisons, manufacturers, pin assignments, logic tables and – where necessary – notes too, all on a single page.

However, this has made it necessary to sacrifice untegrado special-application data which is required by development engineers, in any case, only in ex- treme conditions. Nevertheless, Section 2 is more than just circuiro short-form data compilation since it covers all salient aspects such as current con- sumption, input and output load factors, all of the important transition times and cut-off frequencies. The text of the tabulation is based on the The sequence is listed ascending numerically starting with Section 3 “Case Outlines”: This section now incorporates the new more-representative presentation as already used in the “cmos ” compilation.

This lists random access memories. This lists programmable read-only memories. This lists field-programmable logic assemblies. We would be pleased to hear that this “cmos ‘s tabulation” has become an indispensible tool in your data compilation.


Within the framework of this comparative tabulation we cannot be held responsible for any deviations, however.

And, of course, errors excepted applies to such comprehensive data com- pilations as this. IV alphanumeric list of contents Typ s.

48461012 Contador de 0 9 Con Display

MB NC MB PC MB T MB U6A Fl and FQ relate only to circuits within a family, e. LS output to LS input. Case outline; see section 3 and last page: Pins – Art – Nr. All delay times and frequency apply under the following conditions unless stated otherwise: Frequencies and quiescent current at 6V. Typical values at 5V, maximum values at 5.

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Explanations to the function groups 1. R and S work independent from clock signal asyn- chronous. For logic tables of the various types, see section integrao. See section 2 for logic tables. The length of this pulse is determined by the external values of Clrcuito and R. R returns the flipflop to the stable state irrespective of the state of the inputs A and B. Arrow indicates output carrying a H potential in the stable state. Abbreviations used in the connection drawings J. Inputs on counters, shift registers, decoders etc.

Enable LT Lamp test input on 7-segment decoders a, b, c Outputs of 7-segment decoders MO, M Logic status at A, B Logic status of Q1, Q Logic level depends on other conditions Note ttiat abbreviations found neither here nor in the pin drawings are too complex to permit explanation within the framework of this document. With Preset, J and K 2 flip-flops 2. Non-inverting 4 flip-flops 6 flip-flops 6 flip-flops 8 flip-flops 8 flip-flops 8 flip-flops 8-bit bus interface 8-bit bus interface 9-bit bus interface 1 0-bit bus interface 2.

Inverting 8-bit bus interface 8-bit bus interface 8-bit bus interface 8-bit bus interface 9-bit bus interface 1 0-bit bus interface 2.


Complementary outputs 2 flip-flops 4 flip-flops 4 flip-flops 2. Monostable multivibrators With Schmitt-Trigger inputs 2 retriggerable monostable multivibrators. Other 8-bit diagnostic register. With Preset, Clear, J and K 2 flip-flops 2 flip-flops 2. RS-Latches 4 latches 2. Non inverting 4 latches 8 latches 8-bit bus interface 8-bit bus interface 9-bit bus circuiito 1 0-bit bus interface 2.

Inverting 8-bit 8-bit bus interface 8-bit bus interface 8-bit bus interface 9-bit bus interface 9-bit bus interface bit bus interface 2. circukto


Complementary outputs 4 latches 4 latches Count up 2×4-bit 4-bit 4-bit 4-bit with preset 4-bit with preset 4-bit with preset 4-bit with preset circukto register 4-bit with preset and register 8-bit 8-bit iintegrado preset 8-bit with preset bit bit 3. Parallel outputs 8-bit 8-bit with latch 8-bit with latch bit 4. Comparators 4-bit 8-bit 8-bit 8-bit 8-bit 8-bit with pull-up resistors 1 2-bit address comparator 7474 address comparator with latch. Other Carry generator for counter BCD-to-decimal 4-bit 4-bit 15V 8.

BCD-tosegment 4-bit negativ logic 8. Adders 2×1-bit 4-bit 4-bit 4-bit Kntegrado 7. Priority encoders 8 channel 8 to 3 bit 9 to 4 bit 9. RAM 4×4-bit 16×4-bit x1-bit 9. FIFO first-in first-out memory 64×9-bit 64×9-bit 64×9-bit x9-bit 9. Other 8-bit latch Non-inverting 2×4-bit 2×4-bit Inverting 2×4-bit 4-bit bi-directional 4-bit tri-directional 6-bit 6-bit 8-bit 8-bit with latch 8-bit bi-directional 8-bit bi-directional 8-bit bi-directional with latch 8-bit bi-directional with latch 8-bit bi-directional with latch 8-bit bi-directional with latch 8-bit bi-directional with latch 8-bit bi-directional with latch Inverting and non-inverting 4-bit tri-directional 8-bit bi-directional Nsc Rca Rca Bild Sec.

TP NUm gaxes OD mhiiu yaies OD Inverters 30V Output: TP hanu gaies Val dil-l smd-1 11 11 24 24 24 24 Production Sec. Circkito mhu gaies TP ouiiiinii 1 1 lyvjei iiivtnieisi TP hminu gaies O TP nuk gates TP Driver Output: TP tjuu-io-aecimai aecoaer Val smd-l l 8v 20 20 44 44 Type Bild Sec.

OD BCD-tosegment decoder, outputs active-high TP JK-flip-flops TP D-type flip-flops TP 4-bit full adder TP CA-un gaies Val smd-1 H2n 14 14 30 30 Production Sec. OD 16×4-bit random access memory TP Decade counter TP 8-bit serial shift register Output: TP h-dii Dinary counter TP 4-bit shift register with parallel inputs and outputs TP JK master slave flip-flops Val dil-4 dil-i flat-1 di!

IP JK-flip-flops